This invention relates in general to lateral power transistors and in particular to a lateral Asymmetric Hetero-doped High-voltage MOSFET (AH2MOS) transistors for integrated circuits and for power semiconductor devices.
The operation and cost of an electronic system is improved by reducing the size of transistors and number of packaged devices that make up the system. Many electronic systems save space by forming devices of different types on the same substrate. For example, systems such as cell phones, personal digital assistants and mother boards of personal computers have used separately packaged parts for performing power supply and logic operation. To save space, manufacturers now try to reduce the size of the components in each package, use common process steps for power and logic devices and fabricate power and logic devices on a common semiconductor substrate.
The LDMOS device is a popular transistor for supplying power to electronic systems. It is characterized by a highly doped source disposed in a well or body region that is established by a double diffused implant. Over the source and well is an insulated gate. Spaced from the well is a drift region that holds a drain. The voltage on the gate controls current that flows laterally from the drain, through the drift region and into the source. The drift region is usually lightly doped or at least less doped than either the source or drain.
Logic devices usually have very shallow source and drain regions. In contrast. LDMOS and other high voltage devices often have diffusion regions that extend deep by into the substrate. Such differences present obstacles to using common steps to form power on logic devices on the same substrate. As device features shrink laterally to submicron sizes, the LDMOS device must also scale its vertical dimensions. That presents a problem because many LDMOS and other power devices rely upon high temperatures and long duration diffusion times to establish deep diffusions that support high voltages. Such deep diffusion process steps are not compatible with smaller geometry, shallow junction logic devices. When high voltage devices are added a low voltage, shallow junction deep submicron logic process, the low voltage process limit all diffusion steps to lower temperatures and short cycle times. A conventional thermal diffusion for a power device would destroy the junctions in a deep-submicron CMOS process. One solution to this problem makes the LDMOS first, masks the LDMOS devices, and then makes the low voltage devices in accordance with their lower temperature requirements. However, this will limit LDMOS p-body self-align to gate poly. Therefore, LDMOS devices will have very long gate poly lengths and that feature induces large channel resistance and increases device size, despite using advanced process tools.
In order to solve this problem others have proposed forming power devices by using high dose implants that are made at large implant angles instead of conventional, small angle about ion implants and long thermal diffusions. While such high dose and high angle implants may support a long enough p-body channel for device punch-through, those processes add more steps to the manufacturing process and thus increase the cost of parts. In addition, such processes are often limited by their size of photoresist opening area. It is conventional to use photoresist as a mask to self-align a body implant to the gate polysilicion. However, the thickness of the photoresist will cast a shadow over the implant area when the angle of implant is high and the body opening is small. Others have used a P-well or a combined P-body and P-well instead of the conventional P-body only LDMOS. However, that solution increases the dimension because the P-well is not self-aligned to the gate polysilicon.